Method and system for embedded disk controllers

ABSTRACT

An embedded disk controller comprises a main processor in communication with a first bus. A second processor is in communication with a second bus. An external bus controller (EBC) is in communication with the first bus and in communication with external devices via an external bus interface. A history module is located in the embedded disk controller, communicates with the first bus and the second bus, and at least one of monitors transaction information of one of said external devices and masks information of one of said external devices via the EBC based on setup information, wherein the EBC and the history module are located on at least on of an integrated circuit (IC) and a system on a chip (SOC) with the embedded disk controller.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.10/385,022 filed on Mar. 10, 2003. This application is related to thefollowing U.S. patent applications assigned to the same assignee, filedon even date herewith and incorporated herein by reference in theirentirety:

“METHOD AND SYSTEM FOR SUPPORTING MULTIPLE EXTERNAL SERIAL PORT DEVICESUSING A SERIAL PORT CONTROLLER IN AN EMBEDDED DISK CONTROLLER”, DocketNumber QE1042.US, Ser. No. 10/385,039, with MICHAEL R. SPAUR AND IHN KIMas inventors;

“METHOD AND SYSTEM FOR AUTOMATIC TIME BASE ADJUSTMENT FOR DISK DRIVESERVO CONTROLLERS”, Docket NUMBER QE1040.US, Ser. No. 10/384,992, WITHMICHAEL R. SPAUR AND RAYMOND A. SANDOVAL as inventors;

“METHOD AND SYSTEM FOR USING AN EXTERNAL BUS CONTROLLER IN EMBEDDED DISKCONTROLLERS” Ser. No. 10/385,046 Docket no. QE1035.US with GARY R.ROBECK, LARRY L. BYERS, JOSEBA M. DESUBIJANA, And FREDARICO E. DUTTON asinventors.

“METHOD AND SYSTEM FOR USING AN INTERRUPT CONTROLLER IN EMBEDDED DISKCONTROLLERS”, Ser. No. 10/384,991, Docket No. QE1039.US, with DAVID M.PURDHAM, LARRY L. BYERS and ANDREW ARTZ as inventors.

“METHOD AND SYSTEM FOR MONITORING EMBEDDED DISK CONTROLLER COMPONENTS”,Ser. No. 10/385,042, Docket Number QE1038.US, with LARRY L. BYERS,JOSEBA M. DESUBIJANA, GARY R. ROBECK, and WILLIAM W. DENNIN asinventors.

“METHOD AND SYSTEM FOR COLLECTING SERVO FIELD DATA FROM PROGRAMMABLEDEVICES IN EMBEDDED DISK CONTROLLERS”, Ser. No. 10/385,405, Docket NO.QE1041.US, with MICHAEL R. SPAUR AND RAYMOND A. SANDOVAL as inventors.

BACKGROUND OF THE INVENTION

The present invention relates generally to disk controllers, and moreparticularly to an embedded disk controller that includes a hard diskcontroller, a microprocessor, a digital signal processor, and a servocontroller.

Conventional computer systems typically include several functionalcomponents. These components may include a central processing unit(CPU), main memory, input/output (“I/O”) devices, and disk drives. Inconventional systems, the main memory is coupled to the CPU via a systembus or a local memory bus. The main memory is used to provide the CPUaccess to data and/or program information that is stored in main memoryat execution time. Typically, the main memory is composed of randomaccess memory (RAM) circuits. A computer system with the CPU and mainmemory is often referred to as a host system.

The main memory is typically smaller than disk drives and may bevolatile. Programming data is often stored on the disk drive and readinto main memory as needed. The disk drives are coupled to the hostsystem via a disk controller that handles complex details of interfacingthe disk drives to the host system. Communications between the hostsystem and the disk controller is usually provided using one of avariety of standard I/O bus interfaces.

Typically, a disk drive includes one or more magnetic disks. Each disktypically has a number of concentric rings or tracks on which data isstored. The tracks themselves may be divided into sectors, which are thesmallest accessible data units. A positioning head above the appropriatetrack accesses a sector. An index pulse typically identifies the firstsector of a track. The start of each sector is identified with a sectorpulse. Typically, the disk drive waits until a desired sector rotatesbeneath the head before proceeding for a read or write operation. Datais accessed serially, one bit at a time and typically, each disk has itsown read/write head.

The disk drive is connected to the disk controller that performsnumerous functions, for example, converting digital data to analog headsignals, disk formatting, error checking and fixing, logical to physicaladdress mapping and data buffering. To perform the various functions fortransferring data, the disk controller includes numerous components.

Typically, the data buffering function is used to transfer data betweenthe host and the disk. Data buffering is needed because the speed atwhich the disk drive can supply data or accept data from the host isdifferent than the speed at which the host can correspondingly read orsupply data. Conventional systems include a buffer memory that iscoupled to the disk controller. The buffer memory temporarily storesdata that is being read from or written to the disk drive.

Conventionally, when data is read from the disk drive, a host systemsends a read command to the disk controller, which stores the readcommand into the buffer memory. Data is read from the disk drive andstored in the buffer memory. An ECC module determines the errors thatoccur in the data and appropriately corrects those errors in the buffermemory. Once it is determined that there are no errors, data istransferred from the buffer memory to the host system.

Conventional disk controllers do not have an embedded processor orspecific modules that can efficiently perform the complex functionsexpected from disk controllers.

Conventional disk controllers cannot access plural external memoryhaving different timing characteristics. In addition, conventionalcontrollers do not easily permit use of different bus data width towhich external memory is coupled. In addition, conventional diskcontrollers do not have a built in module that can track bus activityand hence provide valuable information for de-bugging. In conventionaldisk controllers, the disk controller must be coupled to an external busanalyzer to debug and/or monitor bus activity. This process iscumbersome and requires additional pins on the disk controller. Inaddition, conventional monitoring techniques cannot easily isolatecomponents within the disk controller that need to be monitored.Furthermore, conventional disk controllers do not have a dedicatedmodule that controls, prioritizes and generates interrupts.

Therefore, what is desired is an embedded disk controller system thatcan efficiently function in the fast paced, media storage environment.

SUMMARY OF THE INVENTION

An embedded disk controller, comprises a main processor in communicationwith a first bus. A second processor is in communication with a secondbus. An external bus controller (EBC) is in communication with the firstbus and in communication with external devices via an external businterface. A history module is located in the embedded disk controller,communicates with the first bus and the second bus, and at least one ofmonitors transaction information of one of said external devices andmasks information of one of said external devices via the EBC based onsetup information, wherein the EBC and the history module are located onat least on of an integrated circuit (IC) and a system on a chip (SOC)with the embedded disk controller.

In other features of the invention, an interrupt controller modulegenerates a fast interrupt to the main processor based on a fastinterrupt request (FIQ). The EBC includes at least one of a segmentdescriptor register and a device range register, wherein the embeddeddisk controller programs timing characteristics of the external devicesvia the segment descriptor register and the main processor accessesaddress space of the external devices via the device range register. Thehistory module records transaction information on at least one of thefirst bus and the second bus based on a register map. The register mapstores a break point condition value that is set by the first processorand the history module stops recording the transaction information basedon the break point condition value. The history module stores a triggermode field value, wherein the history module records a predeterminednumber of entries after the break point condition value reaches athreshold based on the trigger mode field value.

In other features of the invention, the history module at least one ofstores a read mask field value and stops reading operations based on theread mask field value and stores a write mask field value and stopswrite operations based on the write mask field value. The history modulestores an enable clock slam field value and the history module generatesa signal that stops clocks in the embedded disk controller based on theenable clock slam field value. A servo controller communicates with thesecond processor via a servo controller interface and provides real timeservo controller information to the second processor. The secondprocessor is a digital signal processor (DSP) that communicates with thefirst main processor via an interface.

In other features of the invention, the interrupt controller modulegenerates a regular interrupt based on a regular interrupt request(IRQ). The interrupt controller module includes an interrupt generationmodule that generates a fast interrupt when an FIQ is pending andprocesses an IRQ based on priority when an FIQ is not pending.

In still other features, the systems and methods described above areimplemented by a computer program executed by one or more processors.The computer program can reside on a computer readable medium such asbut not limited to memory, non-volatile data storage and/or othersuitable tangible storage mediums.

Further areas of applicability of the present disclosure will becomeapparent from the detailed description provided hereinafter. It shouldbe understood that the detailed description and specific examples, whileindicating the preferred embodiment of the disclosure, are intended forpurposes of illustration only and are not intended to limit the scope ofthe disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features and other features of the present invention willnow be described. In the drawings, the same components have the samereference numerals. The illustrated embodiment is intended toillustrate, but not to limit the invention. The drawings include thefollowing Figures:

FIG. 1 is a block diagram of a hard disk controller in the prior art;

FIGS. 2A-2B (referred herein as FIG. 2) is a block diagram of anembedded disk controller, according to one aspect of the presentinvention;

FIG. 3 is a block diagram of an external bus controller, according toone aspect of the present invention;

FIGS. 4A, 4B and 4C (referred herein as FIG. 4) show a table withvarious input signals to the external bus controller, according to oneaspect of the present invention;

FIGS. 5A-5C (referred herein as FIG. 5) show a table with various outputsignals from the external bus controller, according to one aspect of thepresent invention;

FIG. 6 is a table showing a register map used by the external buscontroller, according to one aspect of the present invention;

FIGS. 7-9 show various registers with plural fields that are used by theexternal bus controller, according to one aspect of the presentinvention;

FIGS. 10-13 show various timing diagrams for the external buscontroller, according to one aspect of the present invention;

FIG. 14 is a functional block diagram of the external bus controller,according to one aspect of the present invention;

FIG. 15 is a state machine diagram of the external bus controller,according to one aspect of the present invention;

FIG. 16 is a block diagram of an interrupt controller, according to oneaspect of the present invention;

FIGS. 17A-17B (referred herein as FIG. 17) show a table with variousinput signals to the interrupt controller, according to one aspect ofthe present invention;

FIG. 18 is a table showing various output signals from the interruptcontroller, according to one aspect of the present invention;

FIG. 19 is a table showing a register map used by the interruptcontroller, according to one aspect of the present invention;

FIGS. 20-26 show various registers with various fields that are used bythe interrupt controller, according to one aspect of the presentinvention;

FIGS. 27A-27B (referred herein as FIG. 27) show a functional blockdiagram of the interrupt controller, according to one aspect of thepresent invention;

FIG. 28 is a process flow diagram for generating interrupts, accordingto one aspect of the present invention;

FIG. 29 is a process flow diagram for setting interrupt priority,according to one aspect of the present invention;

FIG. 30 is a state machine diagram used by the interrupt controller,according to one aspect of the present invention;

FIG. 31 is a block diagram of history module, according to one aspect ofthe present invention;

FIGS. 32A-1 to 32A4-4 show a table with various input signals to thehistory module, according to one aspect of the present invention;

FIG. 32B is a table showing various output signals from the historymodule, according to one aspect of the present invention;

FIGS. 33-43 show various registers with various fields that are used bythe history module, according to one aspect of the present invention;

FIGS. 44A-44B (referred to herein as FIG. 44) show a functional blockdiagram of the history module, according to one aspect of the presentinvention;

FIG. 45 is a flow diagram of process steps for updating a history stackpointer, according to one aspect of the present invention;

FIGS. 46-49 show various registers with various fields that are used as“mail boxes”, according to one aspect of the present invention;

FIG. 50 shows a flow diagram of process steps for inter-processorcommunication, according to one aspect of the present invention; and

FIGS. 51-53 show various registers with various fields that are used forindirect access of a memory module, according to one aspect of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

To facilitate an understanding of the preferred embodiment, the generalarchitecture and operation of a disk controller will be describedinitially. The specific architecture and operation of the preferredembodiment will then be described.

The disk drive system of FIG. 1 is an example of an internal (hard) diskdrive included in a computer system system. The host computer (notshown) and the disk drive communicate via port 102, which is connectedto a data bus (not shown). In an alternate embodiment (not shown), thedisk drive is an external storage device, which is connected to the hostcomputer via a data bus. The data bus, for example, is a bus inaccordance with a Small Computer System Interface (SCSI) specification.Those skilled in the art will appreciate that other communication busesknown in the art can be used to transfer data between the disk drive andthe host system.

As shown in FIG. 1, the disk drive includes disk controller 101, whichis coupled to SCSI port 102, disk port 114, buffer memory 111 andmicroprocessor 100. Interface 118 serves to couple microprocessor bus107 to microprocessor 100. It is noteworthy that microprocessor 100 isnot on the same chip as disk controller 101. A read only memory (“ROM”)omitted from the drawing is used to store firmware code executed bymicroprocessor 100. Disk port 114 couples disk controller 101 to disk115.

As is standard in the industry, data is stored on disk 115 in sectors.Each sector is byte structured and includes various fields, referred toas the sector format. A typical sector format includes a logical blockaddress (“LBA”) of about four bytes followed by a data field of about512 bytes. The LBA contains position information, for example, cylinder,head and sector numbers. A field for a CRC checksum of 4 bytes typicallyfollows the data field. A subsequent field for a number of ECC bytes,for example 40-80 bytes, is located at the end of the sector.

Controller 101 can be an integrated circuit (IC) (or applicationspecific integrated circuit “ASIC”) that comprises of various functionalmodules, which provide for the writing and reading of data stored ondisk 115. Microprocessor 100 is coupled to controller 101 via interface118 to facilitate transfer of data, address, timing and controlinformation. Buffer memory 111 is coupled to controller 101 via ports tofacilitate transfer of data, timing and address information.

Data flow controller 116 is connected to microprocessor bus 107 and tobuffer controller 108. An ECC module 109 and disk formatter 112 are bothconnected to microprocessor bus 107. Disk formatter 112 is also coupledto data and control port 113 and to data bus 107.

SCSI controller 105 includes programmable registers and state machinesequencers that interface with SCSI port 102 on one side and to a fast,buffered direct memory access (DMA) channel on the other side.

Sequencer 106 supports customized SCSI sequences, for example, by meansof a 256-location instruction memory that allows users to customizecommand automation features. Sequencer 106 is organized in accordancewith the Harvard architecture, which has separate instruction and datamemories. Sequencer 106 includes, for example, a 32-byte register file,a multi-level deep stack, an integer algorithmic logic unit (ALU) andother special purpose modules. Sequencer 106 support's firmware andhardware interrupts schemes. The firmware interrupt allowsmicroprocessor 100 to initiate an operation within Sequencer 106 withoutstopping sequencer operation. Hardware interrupt comes directly fromSCSI controller 105.

Disk formatter 112 is a disk interface controller and performs controloperations when microprocessor 100 loads all required controlinformation and parameter values into a writable control store (WCS) RAM(not shown) and issues a command. Disk formatter 112 executes thecommand with no microprocessor 100 intervention.

Buffer controller 108 can be a multi-channel, high speed DMA controller.Buffer controller 108 connects buffer memory 111 to disk formatter 112and to an ECC channel of ECC module 109, a SCSI channel of SCSIcontroller 105 and micro-controller bus 107. Buffer controller 108regulates data movement into and out of buffer memory 111.

To read data from disk 115, a host system sends a read command to diskcontroller 101, which stores the read commands in buffer memory 111.Microprocessor 100 then read the command out of buffer memory 111 andinitializes the various functional blocks of disk controller 101. Datais read from disk 115 and is passed through disk formatter 112simultaneously to buffer controller 108 and to ECC module 109.Thereafter, ECC module 109 provides the ECC mask for errors, whichoccurred during the read operation, while data is still in buffercontroller 108. The error is corrected and corrected data is sent tobuffer memory 111, and then passed to the host system.

FIG. 2 shows a block diagram of an embedded disk controller system 200according to one aspect of the present invention that not only includesthe functionality of disk controller 101, but also includes variousother features to meet the demands of storage industry. System 200 maybe an application specific integrated circuit (“ASIC”).

System 200 includes a microprocessor (“MP”) 240 (which is also theoverall system processor) that performs various functions describedbelow. MP 240 may be a Pentium® Class processor designed and developedby Intel Corporation® or an ARM processor (for example, ARM966E-S®) orany other processor. MP 240 is operationally coupled to various system200 components via buses 236 and 208. Bus 236 may be an Advanced Highperformance (AHB) bus as specified by ARM Inc. Bus 208 may an AdvancedPeripheral Bus (“APB”) as specified by ARM Inc. The specifications forAHB and APB are incorporated herein by reference in their entirety. Itis noteworthy that the present invention is not limited to anyparticular bus or bus standard.

Arbiter 245 arbitrates access to AHB bus 236, while APB bridge 235 isused to communicate between buses 236 and 208.

System 200 is also provided with a random access memory (RAM) or staticRAM (SRAM) 238 that stores programs and instructions, which allows MP240 to execute computer instructions. MP 240 may execute codeinstructions (also referred to as “firmware”) out of RAM 238.

System 200 is also provided with read only memory (ROM) 237 that storesinvariant instructions, including basic input/output instructions.

MP 240 includes a TAP controller 242 that performs various de-buggingfunctions.

MP 240 is also coupled to an External Bus Interface Bridge (orController) (“EBC” also referred to as “EBI” or “EBI controller”) 228via an external bus interface (“EBI/F”) 227. EBC 228 allows system 200via MP 240 and EBI/F 227 to read and write data using an external bus,for example, a storage device external to system 200, including FLASHmemory, read only memory and static RAM. EBC 228 may be used to controlexternal memory (not shown), as discussed in detail below. EBI/F 227 maybe programmed to interface with plural external devices.

System 200 includes an interrupt controller (“IC”) 207 that can generateregular interrupts (IRQ 207A) or a fast interrupt (FIQ 207B) to MP 240.In one aspect of the present invention, IC 207 is an embedded systemthat can generate interrupts and arbitrates between plural interrupts.IC 207 is described below in detail.

System 200 includes a serial interface (“UART”) 201 that receivesinformation via channel 203 and transmits information via channel 204.

System 200 includes registers 209 that include configuration, systemcontrol, clock and power management information.

System 200 also includes an address break point and history module (alsoreferred to as “history module” or “history stack”) 234 that monitorsactivity on busses 236 and 208 and builds a history stack. Such historystack may be used for debugging, and monitoring plural components ofsystem 200. History module 234 is discussed below in detail.

System 200 also includes a timer module 206 that controlled by MP 240and includes various timers, for example, the “Watchdog timer”.

System 200 is provided with a general purpose input/output (“GPIO”)module 202 that allows GPIO access to external modules (not shown).

System 200 is also provided with a digital signal processor (“DSP”) 229that controls and monitors various servo functions through DSP interfacemodule (“DSPIM”) 210 and servo controller interface 212 operationallycoupled to a servo controller 216.

DSPIM 109 interfaces DSP 229 with MP 240 and updates a tightly coupledmemory module (TCM) 212 (also referred to as “memory module” 212) withservo related information. MP 240 can access TCM 212 via DSPIM 210.

Servo controller interface (“SCI”) 211 includes an APB interface 214that allows SCI 211 to interface with APB bus 208 and allows SC 216 tointerface with MP 240 and DSP 229. SCI 211 also includes DSPAHBinterface 215 that allows access to DSPAHB bus 233. SCI 211 is providedwith a digital to analog/analog to digital converter 213 that convertsdata from analog to digital domain and vice-versa. Analog data 223enters module 213 and leaves as data 222 to a servo drive 221.

SC 212 has a read channel device (RDC) interface 217, a spindle motorcontrol (“SVC”) interface 219, a head integrated circuit (HDIC)interface 218 and servo data (“SVD”) interface 219A.

System 200 also includes a hard disk controller 101A that is similar tothe HDC 101 and includes a code cache 101B.

In one aspect of the present invention, because system 200 includes,dual embedded processors (MP 240 and DSP 229) with dedicated historymodule 234, IC module 207, servo controller and EBC 228, it can performvarious functions independently. This not only saves the resources of MP240 but also improves communication between a host and an externaldevice.

In another aspect, embedded processors (MP 240 and DSP 229) provideindependent real time control, with one processor as the system controlprocessor (MP 240) and the second processor (DSP 229) as a slave to thefirst for real time control of the disk servo mechanism. DSP 229 as aslave also provides real time control for positioning a disk actuator.This includes analyzing error positioning data and outputting errorcorrection data.

Dual processors also provide a real time overlap for processing hostcommands. For example, one processor may move the actuator while theother processor translates the LBA into physical information and queuehost requests.

The dual processors also improve overall performance for the host. Italso allows data recovery when ECC cannot correct data failures. Usingunique data recovery algorithms and error recovery information data maybe recovered if the ECC module 109 fails to dynamically correct thedata.

The following describes the various components of system 200 in detail,according to various aspects of the present invention.

EBC 228

EBC 228 is a slave on AHB bus 236 and adapts the high performance of AHBbus 236 to a slower external bus (not shown) that can support externalmemory (including without limitation, flash memory, ROM, and staticmemory (not shown)). FIG. 3 shows a block diagram of EBC 228 withvarious input signals (300-313) and output signals (314-323). FIG. 4provides a table describing signals 300-313 and FIG. 5 provides a tabledescribing signals 314-323.

In one aspect of the present invention, MP 240 via EBC 228 may accessmultiple devices with different timing characteristics or data width. Atleast a Segment Descriptor register is provided, which specifies thetiming characteristic of each external device. Also provided is at leasta device range register, which specifies the size of the external deviceaddress space. Depending on the external bus data width, EBC 228 mayconvert AHB bus 236 transactions into multiple external bustransactions.

FIG. 6 provides a register map 600 for EBC 228, according to one aspectof the present invention. Register map 600 includes segment descriptorregisters 601, device range registers 602, and EBC 228 configurationregister 603.

Each device segment descriptor register 601 may be formatted the sameway with the same fields. Segment descriptor registers 601 allowfirmware to program timing characteristics for an external memory deviceon an external memory bus. For example, as shown in the table of FIG. 6,four segment descriptor registers 601 may include timing intervals forfour different devices. It is noteworthy that the example in FIG. 6 isonly to illustrate the adaptive aspects of the present invention and notto limit the number of devices to just four. Any number of devices maybe used.

FIG. 7 provides a description of the segment register 601 values. MP 240writes the values in segment registers 601 during initialization.Register(s) 601 includes various values (601A-601G) that allow thefirmware to program timing characteristics for an external memorydevice. Values include a Write Hold Wait State (WHW) 601A, TransactionRecovery Wait States 601B, Setup 2 Wait States (SW2) 601C, Setup 1 WaitStates (SW1) 601D, Data Width (DW) 601E, Write Wait States (WW) 601F andRead Wait State (RW) 601G, as described in FIG. 7.

DW 601E specifies the data width of an external bus device (not shown).A state machine may be used by EBC 228 to use the various register 601values, as shown by the state machine diagram in FIG. 15 and discussedbelow. It is noteworthy that the invention is not limited to the commandterminology of FIG. 7.

FIG. 8 provides a description of device range registers 602. An enable(“EN”) bit 602A is set to access the address range of a device, whilethe device range (DvRng) 602B specifies the number of blocks that may beaddressed within the device address space. MP 240 to allow access to theaddress space within a particular device address initializes devicerange register 602.

FIG. 9 shows the plural fields (603A and 603B) used for configuring EBC228. Device allocation bit 603B specifies the number of devicesallocated on the external bus (not shown) and field 603A is used to readthe external bus width as supported by EBC 228.

FIG. 14 shows a functional block diagram of system 1400 used in EBC 228for supporting plural external devices. Input signals 302 and 307 fromAHB bus 236 are sent to a validation module 1401 that validates theincoming signals. A valid signal is then sent to state machine logic1402.

System 1400 includes a set of registers, for example, HaddrReg 1408,HwriteReg 1411 and HsizeReg 1412 register and their usage is describedbelow.

[0105]FIG. 15 shows a state machine diagram of process steps used bystate machine logic 1402. The following provides a description of theplural states used by state machine logic 1402 to implement the adaptiveaspects of the present invention.

State S0: This is an idle state, until a valid operation on the bus isreceived.

State S1: This is a first stage for decoding an address in HaddreReg1408 to determine which external device if any, is the target for a reador write cycle. After determining the target external device, variouscounter values, as shown in FIG. 15, are loaded during this state.

State S2: This is a second state during which state machine 1402 remainsin this stage until the SW1 601D and TRW 601B values expire to avoiddata contention on the external bus.

State S3: The state machine stays in this state for at least one clockcycle with all external bus controls as being inactive. This state isonly used for sequential write operations.

State S4: During this state the appropriate chip select signal (XCS 317)is asserted while the write enable (XWEn 319) or output enable (XOEn318) are deasserted, until SW2 601C expires.

State S5: The state machine logic 1402 stays in this state until acurrent read or write operation is completed. During this state the chipselect, write enable or out enable signals are asserted. For writecommands, EBC 228 writes data and for read operation, EBC 228 readsdata.

State S6: This state is entered only during write operations and is usedto provide write data hold time. During this state, EBC 228 continues todrive the write data on the external bus while it keeps the write enablesignal de-asserted.

State S7: During this state, registers within EBC 228 are read orwritten.

The relationship between the various states is shown in FIG. 15.

FIGS. 10-13 show various timing diagrams using input signals 300-313 andoutput signals 314-323 with respect to the functional block diagram ofsystem 1400 and the state diagram of FIG. 15.

FIG. 10 shows a diagram for a half word read access to a 16 bit externalbus.

FIG. 11 shows a diagram for a word read access to a 16 bit external bus.

FIG. 12 shows a diagram for a half word write access to a 16 bitexternal bus.

FIG. 13 shows a diagram for a word write access to a 16 bit externalbus.

Interrupt Controller (“IC”) 207

IC 207 synchronizes and prioritizes interrupt signals as a slave on theAPB bus 208. IC 207 handles two types of interrupts, Fast InterruptRequest (“FIQ”) and Interrupt Request (“IRQ”). The interrupts are sentto MP 240. The FIQ 207B is used for critical interrupts as defined by auser or firmware. IRQs 207A are provided for routine interrupts. IC 207provides the interrupts to MP 240 that interrogates IC 207 to retrieve aparticular interrupt with an interrupt vector, as described below. MP240 may clear the interrupt after retrieving the interrupt information.

In one aspect of the present invention, IC module 207, provides FIQ 207Bfor critical interrupts, scans interrupts for priority, preventsinterrupt source lockout (interlock) in the interrupt service and allowsa user to change various interrupt options using firmware.

FIG. 16 shows IC 207 with various input signals (1601-1609) and outputsignals (1610-1614). FIGS. 17 and 18 provide a description of signals1601-1609 and 1610-1614, respectively.

IC module 207 uses plural registers for controlling interrupts. The baseaddress of IC module 207 is specified in APB Bridge 235. When signalPSELIC 1604 from APB bridge 235 is sent to IC module 207, the baseaddress of IC module 207 is detected by APB bridge 235 and IC module 207decodes signals PADDR 1605 and PWRITE 1606 to select the appropriateregister address. IC module 207 examines signal PADDR 1605 forexceptions. An access to an undefined or reserved register addressresults in IC module 207 asserting the PADREXCPT signal 1610 to APBBridge 235. It is noteworthy that this does not change the state of ICmodule 207. Also, access to an undefined “read” address results inPADREXCPT signal 1610 to APB Bridge 235.

FIG. 19 shows a register map 1900 for IC module 207. Register map 1900includes a set of registers 1901 for IRQ control and a register 1904 forFIQ control. Register 1902 stores a current FIQ interrupt and register1903 is used to mask/unmask FIQ ability, via firmware.

FIG. 20 shows details of register 1905 that provides status for an IRQinterrupt. Register 1905 includes field 1905A value for IRQValid. Whenthe bit value for IRQValid is valid (for example, 1) then it indicatesthat IC module 207 has resolved an IRQ interrupt and the Vector Addressfield 1905B is valid.

FIG. 21 shows details of register 1903 that allows firmware to mask theInterrupt ability. FIQ interrupt ability may be enabled or disabled bysetting up FIQInt Mask field 1903B. In addition, by setting field 1903A,IRQ interrupt sources may be masked.

FIG. 22 shows details of various fields used in register 1904, which isan interrupt control register for FIQ source. MK-Read only field 1904Ais a copy of the mask bit from register 1903. Interrupt Request Sent(“IRS”)-Read Only field 1904B is set when MP 240 reads the correspondinginterrupt source as the prioritized interrupt from register 1902.

Interrupt Request Pending (“IRP”)-Read Only field 1904C is set when acorresponding interrupt source is asserted. When IRS 1904B is set, IRP1904C is cleared. In addition, when the source interrupt is masked, IRP1904C may be cleared. Polarity (“PLR”) 1904D is used to specify thepolarity of an interrupt source.

Register 1904 also includes a trigger mode TM value 1904E that specifiesthe mode of an interrupt source signal. Field 1904E specifies whetherthe interrupt signal is edge triggered or level sensitive. Use of TM1904E in register 1904 is discussed below in detail.

FIG. 23 provides various fields that are used in IRQ control register(s)1901, which are interrupt control registers for IRQ sources. MK-Readonly fields 1901A and 1901G are copies of the mask bits from register1903. Interrupt Request Sent (“IRS”)-Read Only fields 1901B and 1901Iare set when MP 240 reads the corresponding interrupt source as theprioritized interrupt from register 1905. Interrupt Request Pending(“IRP”)-Read Only fields 1901C and 1901H are set when a correspondinginterrupt source is asserted. When IRS 1901B or 1901I are set, IRP 1901Cor 1901H are cleared respectively. In addition, when the sourceinterrupt is masked, IRP 1901C and 1901H may be cleared. Polarity(“PLR”) 1901D and 1901J are used to specify the polarity of thecorresponding interrupt sources.

Register(s) 1901 also include trigger mode TM values 1901E and 1901Kthat specify the mode of the interrupt source signals. Field 1901E and1901K specify whether the interrupt signal is edge triggered or levelsensitive. Use of TM 1901E and 1901K in register(s) 1901 is discussedbelow in detail.

Fields 1901F and 1901L contain interrupt vector addresses assigned by MP240 to a corresponding interrupt source. This field specifies a vectoraddress to firmware and specifies the priority of the interrupt with theinterrupt source. The vector field in 1905B is updated when an entry inthe interrupt control register array (described below) that correspondsto an active interrupt is seen as having a higher priority while theregister array is being scanned.

FIG. 24 shows the field used by register 1902. Field 1902A, when validindicates that there is a fast interrupt request asserted to MP 240.Field 1902A is cleared when register 1902 is read.

FIG. 25 shows the fields used in register 1907. Register 1907 is acontrol register showing when an interrupt has been sent. Field 1907A isused for a FIQ source and field 1907B is used for IRQ sources, asdescribed below.

FIG. 26 shows the fields for register 1906 used for pending interrupts.Field 1906A is used for an FIQ source and field 1906B is used for IRQsources, as described below.

FIG. 27 shows a functional block diagram of system 2000 used by ICmodule 207, in various adaptive aspects of the present invention.

FIQ Interrupts

Input signal 1608 from a FIQ source is sent to module 2005. Module 2005selects either the FIQ source signal, or a TestSource signal dependingon the state of ICIntTestControl 2017. If the FIQ source signal isselected, then it is synchronized by raw interrupt synchronizationmodule 2006. The synchronized signal is sent for FIQ registration to FIQregistration module 2007. Module 2007 includes registers 1904, and 1902.

Signal 1607 is sent to mask module 2004 (that includes register 1903)and to FIQ IC module 2008. Mask module 2004 sends the mask (1903A) toFIQ IC module 2008, which then sends a signal to interrupt generationmodule 2009. Interrupt generation module 2009 also receives input fromIRQ Scanner 2011 and based upon the priority of the request, aninterrupt is generated, for example FIQn 1611, SysInt 1614 and IRQn1613.

When FIQIRP 1904C is set, then a fast interrupt is asserted. Theinterrupt request signal remains asserted until MP 240 reads register1902. When register 1902 is read, FIQn signal 1611 is de-asserted bysetting FIQIRS 1904B and clearing FIQIRP 1904C.

In one aspect, another interrupt request cannot be made until FIQIRS1904B is cleared as follows:

If FIQ interrupt source as defined by TM 1904E is level sensitive thenthe firmware ensures that the FIQ interrupt source is de-asserted andthen an end of interrupt (“EOI”) is sent to IC 207 to clear the FIQIRS1904B state; or

If the FIQ interrupt source as defined by TM 1904E is edge triggered,the firmware need only read register 1902, FIQIRP 1904C is cleared andFIQIRS 1904B is set. In edge triggered mode, FIQIRS clears when theinterrupt source de-asserts. The next interrupt does not occur until theinterrupt source signal de-asserts, and asserts again.

IRQ Interrupts

Incoming IRQESOURCE signals 1609 is received by module 2002. Module 2002selects either the IRQESOURCE signal, or TestSource signals depending onthe state of ICTestControl 2015. If the IRQESOURCE signals are selected,then they are synchronized by raw interrupt synchronization module 2003.The synchronized signals are sent for IRQ registration to IRQregistration module 2013. IRQ interrupt registration module 2013 setsthe field 1906B in register 1906. Signal 1607 is sent to mask module2004 (that includes register 1903) and to IRQ Interrupt RegistrationModule 2013. Mask module 2004 sends the mask (1903A) to IRQ InterruptRegistration module 2013, which then sends signals to the IRQ PriorityEvaluation And Scanner module 2011 (also referred herein as “IRQ Scanner2011”). It is noteworthy that firmware may mask an interrupt before itis sent to MP 240. This de-registers the interrupt by clearing field1906B.

For each possible interrupt input, information regarding that interruptis stored in IRQ register control array 1901. Register control array1901 includes vector values (1901F and 1901L), TM values (1901E and1901K) and PLR values (1901D and 1901J) for each interrupt source, i.e.even and odd source. MP 240 may write the foregoing values in registercontrol array 1901. Vector values 1901F and 1901L provide the offset forfirmware to access the interrupt handler (Not shown) and establish thepriority of the interrupt within plural interrupt sources, for example,16 IRQ sources. It is noteworthy that the invention is not limited to 16IRQ sources. In one aspect, the highest vector value is given thehighest priority. When one of the registers in register control array1901 is read then, the mask, IRS, IRP, Vector, TM and PLR values arealso read at the same time. Output 2012 from register control array 1901is sent to IRQ scanner 2011 that scans the vector values, as describedbelow. IRQ scanner 2011 provides an input 2011A to interrupt generator2009 that generates IRQn 1613.

When MP 240 retrieves the IRQ interrupt from IC module 207 it readsregister 1905 which sets the IRQIRS bit (1901B or 1901I) associated withthe interrupt source in register 1905, which prevents the same interruptsource from generating another interrupt until the IRQIRS bit iscleared.

In one aspect, another interrupt from the same source cannot be madeuntil IRQIRS (1901B or 1901I) is cleared as follows:

If the IRQ interrupt source is defined by TM 1901E or 1901K as levelsensitive then the firmware ensures that the IRQ interrupt source isde-asserted. Thereafter, an end of interrupt (“EOI”) is sent to IC 207to clear the IRQIRS 1901B or 1901I state; or

If the IRQ interrupt source is defined by TM 1901E or 1901K as edgetriggered, the firmware need only read register 1905. IRQIRP 1901C or1901H is cleared and IRQIRS 1901B or 1901I is set. In edge triggeredmode, IRQIRS clears when the interrupt source de-asserts. The nextinterrupt does not occur until the interrupt source signal de-asserts,and asserts again.

FIG. 28 is a flow diagram for IRQ generation with respect to thefunctional diagram of FIG. 27 and the various registers described above.

In step S2800, an IRQ signal 1609 is received from an interrupt source.

In step S2801, IRQ signal 1609 is selected by logic 2002.

In step S2802, valid IRQ signal 1609A is synchronized by synchronizationmodule 2003.

In step S2803, synchronized IRQ signal 1609B is registered by IRQinterrupt registration module 2013.

In step S2804, registers in register control array 1901 are read.

In step S2805, vector values are scanned (discussed below with respectto FIG. 29).

In step S2806, based on the vector values, output interrupt signal 1613is sent to MP 240.

FIG. 29 is a flow diagram showing executable process steps used by IRQscanner 2011.

In step S2900, IRQ scanner 2011 receives register values 2012 fromregister control array 1901 and IRQESOURCE 2013A from IRQ interruptregistration module 2013. IRQ scanner 2011 receives vector values fromregister control array 1901. IRQ scanner 2011 examines each interruptduring every interrupt cycle

In step S2901, the process determines if an interrupt is being sent sentas used here includes “pending” interrupts). If an interrupt is beingsent (or pending), then in step S2902, IRQ scanner 2011 compares thevector values of the interrupt being sent (or pending) with the scannedvector values of every other active interrupt input in a given interruptcycle.

In step S2903, IRQ scanner 2011 replaces the previous vector values ifthe most current vector values have higher priority.

If an interrupt is not being sent (or pending) in step S2901, then instep S2904, IRQ scanner 2011 loads the current vector values from anactive interrupt input from S2901 and the process moves to step S2902.

FIG. 30 shows a state diagram for interrupt control, according to oneaspect of the present invention. It is noteworthy, that although thestate diagram of FIG. 30 shows that it is for IRQ interrupts, the samewill also apply for FIQ interrupts. State diagram includes three states3000, 3001 and 3002. State 3000 is for receiving an interrupt request.State 3001 is an interrupt pending state and state 3002 is an interruptsent state. Based on the foregoing discussions regarding FIGS. 16-29,the state transitions of state diagram in FIG. 30 are self-explanatory.

In one aspect of the present invention, a fast interrupt scheme isprovided so that for critical interrupts, MP 240 does not have to wait.

In another aspect of the present invention, interrupt priority isestablished efficiently by a scanning process.

In yet another aspect of the present invention, firmware can changepriority and mask interrupts from any source, providing flexibility to auser and also optimizes MP 240 usage.

In another aspect of the present invention, use of TM values preventsinterlocking of interrupt service by MP 240.

History Module 234

History module 234 is a peripheral on APB Bus 208 that recordstransaction information over either AHB Bus 236 and/or APB Bus 208. Therecorded information may be used for debugging and analyzing firmwareand hardware problems. History module 234 is set up and initiatedthrough APB Bridge 235 and information from History module 234 isextracted through APB Bridge 235. History module 234 includes abuffer(s) (not shown) for reading and writing recorded information.

FIG. 31 shows a top-level block diagram of History Module 234 withplural input and output signals.

FIGS. 32A-1, 32A-2, 32A-3, 32A-4 and 32B provide a description of theinput and output signals, respectively.

FIG. 33 provides a listing of a register map 3309 used by History Module234. Register map 3309 includes various registers that are used forsetting up History Module 234 recording and control conditions. The baseaddress of History Module 234 is specified in APB bridge 235 and whenPSELABPHS 3108 is asserted to History Module 234, the base address hasbeen detected by APB bridge 235. History Module 234 decodes PADDR 1605and PWRITE 1606 to select accessed memory mapped registers.

FIG. 34 provides a table for register 3300 with the various fields(3300A-3300J) to control and set up History Module 234. SelectMask 3300Afield if set isolates certain components in system for monitoring andrecording by History Module 234. Firmware can also filter read and/orwrite operations. By setting fields 3300B and 3300C, read and/or writeoperations are not recorded by History Module 234.

Field 3300J defines break point conditions for History Module 234. Breakpoint conditions are those, which stop recording/monitoring by HistoryModule 234. Field 3300I enables break points, while break point testingstops after a break point is detected, if field 3300E is set.

Trigger mode field 3300G specifies the number of entries made in aHistory Module 234 buffer after a break point condition is detected.

FIG. 35 shows register 3500 that stores a history stack pointer(referred to as “HstryStkPtr” or “HSP”) 3501. HSP 3501 provides theaddress of the next entry at a given time, for either reading from, orwriting to, the history module 234 buffer.

HSP 3501 may be zero at the beginning of a recording session. Firmwarehas the flexibility to change HSP 3501 values. In one aspect, firmwaremay set this value to zero. HSP 3501 allows the firmware to recover arecording regardless of the reason why a recording session stopped. HSP3501 is incremented each time an entry is accessed from the historystack buffer.

FIG. 36A shows register 3603 that provides the address break pointpattern for address break point testing. Field 3602 provides the addressbreak point pattern for such break point testing.

FIG. 36B shows a data/address break point pattern register 3600(DataAdrBPPReg 3600) that stores break point data pattern (“BPData”)field 3601. BPDATA field 3601 is compared against a data and addressbreak point condition. Based on the selected break point condition andthe comparison a break point sets and recording by History Module 234stops when the trigger mode is satisfied.

FIG. 37 shows register 3700 that includes recorded AHB bus 236information in history module 234 buffer. When register 3700 is read,history stack pointer 3501 is incremented.

FIG. 38 shows register 3800 that includes recorded APB bus 208 addressinformation (similar to register 3700). Register 3500 is incrementedafter register 3800 is read.

FIG. 39 shows a control history register 3900 that includes recorded AHBbus 236 information. Register 3500 is incremented after register 3900 isread.

FIG. 40 shows a control history register 4000 that includes recorded APBbus 208 information. Register 3500 is incremented after register 4000 isread.

FIG. 41 shows register 4100, which includes AHB bus 236 or APB bus 208data specified by the pointer value in register 3500. Register 3500 isincremented after register 4100 is read.

FIG. 42 shows register 4200 that includes a Clear History Stack Buffer(“CHSB”) field 4201. Setting CHSB field 4201 clears HSP 3501. CHSB 4201is set while zero data is being written to buffers 4313 to 4315.

FIG. 43 shows register 4300 that includes a “Set EnableRecord” field4300A that may be set by firmware. When field 4300A is set, Historymodule 234 starts recording and the recording stops when field 4300A iscleared.

FIG. 44 is a functional block diagram, of history module 234 that willbe described below with respective to various inventive aspects of thepresent inventions. History module 234 may be setup by firmware toperform its various function. Control information is written to register3300. If a break point is desired for address and/or data, or addressrange, then MP 240 sets registers 3600 and 3603.

To start history module 234, field 4300A of register 4300 is set, thatallows recording when signals HREADY 307 or PENABLE 1607 are asserted.In one aspect of the present invention, history module 234 may recorddata simultaneously for buses 236 and 208. This allows history module234 to write in buffers 4313, 4314 and 4315. Although FIG. 44 showsthree buffers for address, control and data information, the inventionis not limited to the number of buffers used by history module 234. Forexample, only one or more buffers may be used to implement the adaptiveaspects of the present invention.

History module 234 continues to make entries until a break point (orevent) is reached as defined by fields 3300I and 3330J in register 3300or field 4300A is cleared by firmware, as discussed below in detail.

Valid Recorded Entry: Before recording, buffers 4313, 4314 and 4315 arecleared by firmware issuing a “clear History stack Buffer Access 4201command. All valid entries in buffer 4314 are cleared. When recording,field 4201 is toggled each time an entry is made in buffers 4313-4315.

Break Point and Break Point Interrupt: Firmware can set field 3300I toenable a break point defined by break point condition field 3300J. Eventcontrol module 4336 generates field 4300A value that is sent toflip-flop module 4323. Firmware can set field 4300A value that enablesflip-flop module 4323. History module 234 tests for break pointcondition 3300J in every clock cycle as defined by firmware.

When history module 234 detects the defined break point condition thenit stops recording bus transactions based on TM value 3300G and aninterrupt may be generated, as discussed below. After a break point isdetected, history module 234 stops recording and based on field 3300Esetting either continues to test for the break condition or stopstesting for the break point condition.

An interrupt is generated based on the detection of the break pointcondition and if field 3300F is set, after the interrupt source isenabled in IC module 207.

Break points may be set for address and/or data or address range basedon fields 3601 and 3602. Firmware may also send a “Clear Enable Recordstatus” field 4300A to trigger a firmware break point, if a firmwarebreak point condition is set in 3300J.

Clock Slam: When a break point condition is detected, and if field 3300Dis enabled (Enable clock Slam), history module 234 asserts signalClkSlam 4343 to clock control via flip-flop module 4340. Break pointcondition 3300J′, which indicates that a break point condition hasoccurred, is sent to event control module 4336 with trigger mode value3300G. This stops all the clocks in system 200. This signal remainsasserted until system 200 is reset. This allows system 200 componentinformation to be scanned out for analysis and diagnosis using standarddebugging tools.

Filter Control: History module 234 can selectively filter out system 200components based on filter control command 4324. Filter control command4324 is based on select mask field 3300A in register 3300. If field3300A is set then transactions related to, a specific peripheral(s) orslave (depending on the bus) is not recorded.

Trigger Mode

Trigger mode field 3300G specifies the number of entries that are madein buffers 4313-4315 after a break point condition has been detected. Inone aspect, field 3300G may be set so that history module 207 stopsrecording within a single clock cycle, or may continue to record apre-defined amount of data before stopping.

Starting and Stopping Recording

History module 234 starts and stops recording based on register 4300fields. Field 4300A when set to “EnableRcrdReg”, allows history module234 to record. Setting “Clear Enable Record and Status” bit in field4300A stops history module 234 from recording and break point testing,unless specified otherwise by firmware.

Bus (208 and 236) transactions are recorded when EnableRcrdReg is set.Mux 4324 samples signals HREADY 307 and PENABLE 1603. The signalsindicate that a valid transaction is on the bus that may be recordedunless masked by field 3300A.

History Stack Pointer

History stack pointer 3500, as shown in FIG. 35, keeps track of wherethe next entry in buffer 4313-4315 will be made while history module 234is recording. When an entry is made in buffers 4313-4315, pointer 3501is updated. When history module 234 stops making entries in buffers4313-4315, the value of 3501 points to the last entry plus one.

Extracting Recorded History Information

As stated above, when recording stops, history stack pointer 3501 pointsto the “oldest recorded entry”. MP 240 bus master (not shown) reads thehistory address buffer 4313 and history module 234 places the recordedentry into register 4300 (FIG. 43) and history stack pointer nowpointing to the last entry read is incremented by one. APB bridge 235returns the recorded entry to MP 240 bus master and it increments it'sread count. After buffer 4313 is read, the same process is applied tobuffers 4314 and 4315.

FIG. 45 shows a flow diagram of executable process steps in historymodule 207 for recording bus transactions in system 200, according toone aspect of the present invention.

Turning in detail to FIG. 45, is step S4500, the process sets upregisters for recording. Field 4300A is set to “EnableRcrdReg” (alsoreferred to as “EnRcrdReg” in FIG. 43) to record transactions.

In step S4501, the process determines if field 3300E is set to enableany break point testing. Field 3300J in register 3300 may be used tospecify break point conditions.

In step S4502, transactions are recorded. Bus (208 and 236) transactionsare recorded when EnableRcrdReg field 4300 is set. Signals HREADY 307and PENABLE 1603 are sampled by Mux 4324. The signals indicate that avalid transaction is on the bus that may be recorded unless masked byfield 3300A. When an entry is made in buffers 4313-4315, pointer 3501 isupdated. When history module 234 stops making entries in buffers4313-4315, the value of 3501 points to the last entry plus one.

In step S4503, based on whether break point condition testing isenabled, history module 234 tests for break point conditions. Based onthe setting of EnBPStp 3300E, history module 234 may continue or stopbreak point condition testing after a particular break point isencountered.

In step S4504, the process determines the value of TM field 3300G. Thissets the amount of data that is to be recorded after a break pointcondition is detected. It is noteworthy that steps S4502-4504 may occursimultaneously.

In step S4505, recording is stopped and field 4300A is cleared.

In step S4506, recorded information is extracted. MP 240 bus master (notshown) reads the history address buffer 4313 and history module 234places the recorded entry into register 4327 (FIG. 44A) and historystack pointer 3501 is incremented by one. APB bridge 235 returns therecorded entry to MP 240 bus master and it increments its' read count.After buffer 4313 is read, the same process is applied to buffers 4314and 4315.

In one aspect of the present invention, history module 234 providesvisibility to transactions on the internal AHB Bus 236 or APB Bus 208.

In one aspect of the present invention, history module 234 selectsspecific slave or peripheral transactions for recording based on a slaveor peripheral mask. This allows selective monitoring of system 200components.

In yet another aspect of the present invention, the process describedabove provides break point conditions for stopping History module 234recording. However, external break point signal may be continuallyprovided after recording stops. In addition, break point conditions maybe provided for an Address/Data break point and an Address Range breakpoint.

In another aspect of the present invention, an external analyzer is notrequired to record bus transactions. This saves pins and the effortrequired connecting system 200 to an external device so that itscomponents can be monitored.

Firmware Synchronization

DSPIM 210 provides an interface for communication between MP 240 and DSP229 as a bridge between APB bus 208 and DSPAHB bus 233. DSPIM 210provides an IN/OUT register file for passing command and statusparameters between MP 240 and DSP 229. FIGS. 46 and 47 show registersthat are used for MP 240 and DSP 210 to communicate with each other.Register 4600 and 4700 are addressable from APB bus 208 and DSPAHB bus233. Registers 4600 and 4700 provide a “mail box” for exchange ofinformation between MP 240 and DSP 229. Register 4600 can be read andwritten by MP 240. MP 240 can only read register 4700, while DSP 229 mayread or write. An attempt by MP 240 to write into register 4700 resultsin declaration of “address exception” by DSPIM 210. Contents ofregisters 4600 and 4700 are based on firmware and user definedparameters.

MP 240 writes in register 4600 and interrupt is sent to DSP 229. MP 240sets field 4900C in status register 4900, which generates an interruptto DSP 229.

FIG. 50 shows a flow diagram of communication between MP240 and DSP 229using IN/Out registers 4600 and 4700, respectively.

In step S5000, MP 240 send information to DSP 229.

In step S5001, MP240 writes the information (or address of theinformation) in register 4600.

In step S5002, MP 240 sets field 4900C and generates an interrupt forDSP 229.

In step S5003, DSP 229 services the interrupt by reading register 4600and clears field 4900C.

In step S5004, register 4600 is again available for MP 240 to write intoregister 4600.

DSPIM 210 is operationally coupled to memory module 212 via interface230. MP240 and DSP 229 for storing firmware control instructions and anyother information may use memory module 212. Interface 230 allows APBbus 208 to access memory module 212 while DSPIM 210 executes firmwareinstructions.

Memory module 212 is shared using registers 4600, 4700 and semaphoreregister 5100 shown in FIG. 51. Semaphore register 5100 field 5100Aprovides firmware interlock when MP 240 acquires the semaphore.Semaphore register 5100 field 5100B provides hardware interlock when MP240 acquires the semaphore. DSP 229 cannot execute a write access to anyregister except register 5100 or a status register.

Memory module 212 uses an indirect access register 5200 that facilitatescommunication between DSP 229 and MP 240 without using any counters.Memory module 212 uses at least a FIFO buffer from where data may beread and/or written. Memory module 212 uses register 5300 (FIG. 53) thatincludes FIFO data. MP 240 sets up field 5200A that allows indirectaccess. Field 5200G indicates the starting address of memory module 212.Each access to register 5300 updates field 5200G.

An indirect read transaction may be initiated by setting up field 5200Aand 5200C. Each time register 5300 is accessed, the address in field5200F is updated. If field 5200C is set then it indicates that the readaccess is a sequence of continual read accesses that keeps memory module212 FIFO (not shown) full.

An indirect write access may be initiated by setting field 5200A and5200B. After the indirect access, register 5300 is updated with datathat is written into memory module 212. Each time data is written intoregister 5300, DSPIM 210 writes data into memory module 212.

One advantage of providing the mail-box” concept is that no writeconflict occurs between MP 240 and DSP 229.

In one aspect, MP 240 and/or DSP 229 do not have to gain ownership andthen relinquish ownership (clear) of any registers to communicate witheach other. This saves performance time and improves overall efficiency,because the registers are dedicated.

In another aspect of the present invention, indirect access is availableto access memory module 212.

In another aspect of the present invention, the IN/Out mailboxenvironment may be used to efficiently run test cases. MP 240 usingAssembler or any other language may run test cases. A sub-set of testinstructions may be executed by DSP 229. The mailboxes have a buffer(not shown) that keeps a real-time picture of a test case. When the testis complete, mail-boxes are unloaded and a report may be generated thatcan be used for bug fixing and analysis.

Although the present invention has been described with reference tospecific embodiments, these embodiments are illustrative only and notlimiting. Many other applications and embodiments of the presentinvention will be apparent in light of this disclosure and the followingclaims.

1. An embedded disk controller, comprising: a main processor incommunication with a first bus; a second processor in communication witha second bus; an external bus controller (EBC) in communication with thefirst bus and in communication with external devices via an external businterface; and a history module that is located in the embedded diskcontroller, that communicates with the first bus and the second bus, andthat at least one of monitors transaction information of one of saidexternal devices and masks information of one of said external devicesvia the EBC based on setup information, wherein the EBC and the historymodule are located on at least one of an integrated circuit (IC) and asystem on a chip (SOC) with the embedded disk controller.
 2. Theembedded disk controller of claim 1 further comprising an interruptcontroller module that generates a fast interrupt to the main processorbased on a fast interrupt request (FIQ).
 3. The embedded disk controllerof claim 1 wherein the EBC includes at least one of a segment descriptorregister and a device range register, wherein the embedded diskcontroller programs timing characteristics of the external devices viathe segment descriptor register and the main processor accesses addressspace of the external devices via the device range register.
 4. Theembedded disk controller of claim 1 wherein the history module recordstransaction information on at least one of the first bus and the secondbus based on a register map.
 5. The embedded disk controller of claim 4wherein the register map stores a break point condition value that isset by the first processor and the history module stops recording thetransaction information based on the break point condition value.
 6. Theembedded disk controller of claim 5 wherein the history module stores atrigger mode field value, wherein the history module records apredetermined number of entries after the break point condition valuereaches a threshold based on the trigger mode field value.
 7. Theembedded disk controller of claim 1 wherein the history module at leastone of: stores a read mask field value and stops reading operationsbased on the read mask field value; and stores a write mask field valueand stops write operations based on the write mask field value.
 8. Theembedded disk controller of claim 1 wherein the history module stores anenable clock slam field value and the history module generates a signalthat stops clocks in the embedded disk controller based on the enableclock slam field value.
 9. The embedded disk controller of claim 1further comprising a servo controller that communicates with the secondprocessor via a servo controller interface and provides real time servocontroller information to the second processor.
 10. The embedded diskcontroller of claim 1 wherein the second processor is a digital signalprocessor (DSP) that communicates with the first main processor via aninterface.
 11. The embedded disk controller of claim 2 wherein theinterrupt controller module generates a regular interrupt based on aregular interrupt request (IRQ).
 12. The embedded disk controller ofclaim 11 wherein the interrupt controller module includes an interruptgeneration module that generates a fast interrupt when an FIQ is pendingand processes an IRQ based on priority when an FIQ is not pending.